The converter of claim 1, wherein m≧n.ġ0. The converter of claim 1 further comprising a multiplexer, which receives data from the outputs of the first data receiver and the second data receiver and connects to the selector for determining one of the outputs of the first data receiver and the second data receiver as the parallel data output.ĩ. The converter of claim 6, wherein the pre-register in each conversion cycle shifts the stored first m bit(s) back to one of the first data receiver and the second data receiver at a time selected from the last phase clock and the rising edge of the last phase clock referred thereby.Ĩ. The converter of claim 5, wherein the pre-register in each conversion cycle refers to m phase clocks to store in order the first m bit(s) in the n-bit parallel data.ħ. The converter of claim 1, wherein the flip-flop(s) of the pre-register is D-type flip-flop(s) without enable control.Ħ.
The converter of claim 3, wherein the first data receiver and the second data receiver refer to the same n phase clocks.ĥ. The converter of claim 2, wherein the D-type flip-flops for storing corresponding bits of the n-bit parallel data in the first data receiver and the second data receiver refer to the same phase clock for latching the serial data.Ĥ. The converter of claim 1, wherein the flip-flops of the first data receiver and the second data receiver are D-type flip-flops with enable control.ģ. A serial-to-parallel data converter for converting a serial data into a n-bit parallel data, comprising: a first data receiver, composed of n flip-flops for latching the n-bit parallel data referring n phase clock signals in a conversion cycle a second data receiver, composed of n flip-flops with inputs connected in parallel with inputs of the first data receiver, for latching the n-bit parallel data by referring said n phase clock signals in said conversion cycle a pre-register, composed of m flip-flop(s) for latching the first m bit(s) of the n-bit parallel data and output(s) thereof connected to the inputs of flip-flops in the first data receiver and the second data receiver corresponding to the first m bit(s) wherein the inputs of the pre-register receive the serial data, and the first m bit(s) is shifted back to one of the first data receiver and the second data receiver before each conversion cycle ends and a selector, connected to the flip-flops of the first data receiver and the second data receiver for selecting one of the first data receiver and the second data receiver for serial data conversion and the other for parallel data output.Ģ.
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